Jose
6e65c6eccc
new file: include/_hal_uart_isr.c new file: include/hal_adc.c new file: include/hal_adc.h new file: include/hal_aes.h new file: include/hal_assert.c new file: include/hal_assert.h new file: include/hal_board.h new file: include/hal_board_cfg.h new file: include/hal_ccm.h new file: include/hal_defs.h new file: include/hal_dma.c new file: include/hal_dma.h new file: include/hal_drivers.c new file: include/hal_drivers.h new file: include/hal_flash.c new file: include/hal_flash.h new file: include/hal_key.c new file: include/hal_key.h new file: include/hal_lcd.c new file: include/hal_lcd.h new file: include/hal_led.c new file: include/hal_led.h new file: include/hal_mac_cfg.h new file: include/hal_mcu.h new file: include/hal_oad.c new file: include/hal_oad.h new file: include/hal_ota.c new file: include/hal_ota.h new file: include/hal_rpc.h new file: include/hal_sleep.c new file: include/hal_sleep.h new file: include/hal_startup.c new file: include/hal_timer.c new file: include/hal_timer.h new file: include/hal_types.h new file: include/hal_uart.c new file: include/hal_uart.h
810 lines
24 KiB
C
810 lines
24 KiB
C
/**************************************************************************************************
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Filename: _hal_uart_dma.c
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Revised: $Date: 2010-04-01 18:14:33 -0700 (Thu, 01 Apr 2010) $
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Revision: $Revision: 22068 $
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Description: This file contains the interface to the H/W UART driver by DMA.
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Copyright 2006-2010 Texas Instruments Incorporated. All rights reserved.
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IMPORTANT: Your use of this Software is limited to those specific rights
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granted under the terms of a software license agreement between the user
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who downloaded the software, his/her employer (which must be your employer)
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and Texas Instruments Incorporated (the "License"). You may not use this
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Software unless you agree to abide by the terms of the License. The License
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limits your use, and you acknowledge, that the Software may not be modified,
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copied or distributed unless embedded on a Texas Instruments microcontroller
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or used solely and exclusively in conjunction with a Texas Instruments radio
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frequency transceiver, which is integrated into your product. Other than for
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the foregoing purpose, you may not use, reproduce, copy, prepare derivative
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works of, modify, distribute, perform, display or sell this Software and/or
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its documentation for any purpose.
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YOU FURTHER ACKNOWLEDGE AND AGREE THAT THE SOFTWARE AND DOCUMENTATION ARE
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PROVIDED “AS IS” WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED,
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INCLUDING WITHOUT LIMITATION, ANY WARRANTY OF MERCHANTABILITY, TITLE,
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NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL
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TEXAS INSTRUMENTS OR ITS LICENSORS BE LIABLE OR OBLIGATED UNDER CONTRACT,
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NEGLIGENCE, STRICT LIABILITY, CONTRIBUTION, BREACH OF WARRANTY, OR OTHER
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LEGAL EQUITABLE THEORY ANY DIRECT OR INDIRECT DAMAGES OR EXPENSES
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INCLUDING BUT NOT LIMITED TO ANY INCIDENTAL, SPECIAL, INDIRECT, PUNITIVE
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OR CONSEQUENTIAL DAMAGES, LOST PROFITS OR LOST DATA, COST OF PROCUREMENT
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OF SUBSTITUTE GOODS, TECHNOLOGY, SERVICES, OR ANY CLAIMS BY THIRD PARTIES
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(INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF), OR OTHER SIMILAR COSTS.
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Should you have any questions regarding your right to use this Software,
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contact Texas Instruments Incorporated at www.TI.com.
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**************************************************************************************************/
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/*********************************************************************
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* INCLUDES
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*/
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#include "hal_types.h"
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#include "hal_assert.h"
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#include "hal_board.h"
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#include "hal_defs.h"
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#include "hal_dma.h"
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#include "hal_mcu.h"
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#include "hal_uart.h"
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#if defined MT_TASK
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#include "mt_uart.h"
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#endif
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#include "osal.h"
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/*********************************************************************
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* MACROS
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*/
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//#define HAL_UART_ASSERT(expr) HAL_ASSERT((expr))
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#define HAL_UART_ASSERT(expr)
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#if defined HAL_BOARD_CC2430EB || defined HAL_BOARD_CC2430DB || defined HAL_BOARD_CC2430BB
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#define HAL_UART_DMA_NEW_RX_BYTE(IDX) (DMA_PAD == LO_UINT16(dmaCfg.rxBuf[(IDX)]))
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#define HAL_UART_DMA_GET_RX_BYTE(IDX) (HI_UINT16(dmaCfg.rxBuf[(IDX)]))
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#define HAL_UART_DMA_CLR_RX_BYTE(IDX) (dmaCfg.rxBuf[(IDX)] = BUILD_UINT16((DMA_PAD ^ 0xFF), 0))
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#else
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#define HAL_UART_DMA_NEW_RX_BYTE(IDX) (DMA_PAD == HI_UINT16(dmaCfg.rxBuf[(IDX)]))
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#define HAL_UART_DMA_GET_RX_BYTE(IDX) (LO_UINT16(dmaCfg.rxBuf[(IDX)]))
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#define HAL_UART_DMA_CLR_RX_BYTE(IDX) (dmaCfg.rxBuf[(IDX)] = BUILD_UINT16(0, (DMA_PAD ^ 0xFF)))
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#endif
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/*********************************************************************
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* CONSTANTS
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*/
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// UxCSR - USART Control and Status Register.
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#define CSR_MODE 0x80
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#define CSR_RE 0x40
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#define CSR_SLAVE 0x20
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#define CSR_FE 0x10
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#define CSR_ERR 0x08
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#define CSR_RX_BYTE 0x04
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#define CSR_TX_BYTE 0x02
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#define CSR_ACTIVE 0x01
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// UxUCR - USART UART Control Register.
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#define UCR_FLUSH 0x80
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#define UCR_FLOW 0x40
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#define UCR_D9 0x20
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#define UCR_BIT9 0x10
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#define UCR_PARITY 0x08
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#define UCR_SPB 0x04
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#define UCR_STOP 0x02
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#define UCR_START 0x01
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#define UTX0IE 0x04
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#define UTX1IE 0x08
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#define P2DIR_PRIPO 0xC0
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// Incompatible redefinitions result with more than one UART driver sub-module.
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#undef PxOUT
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#undef PxDIR
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#undef PxSEL
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#undef UxCSR
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#undef UxUCR
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#undef UxDBUF
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#undef UxBAUD
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#undef UxGCR
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#undef URXxIE
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#undef URXxIF
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#undef UTXxIE
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#undef UTXxIF
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#undef HAL_UART_PERCFG_BIT
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#undef HAL_UART_Px_RTS
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#undef HAL_UART_Px_CTS
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#undef HAL_UART_Px_RX_TX
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#if (HAL_UART_DMA == 1)
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#define PxOUT P0
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#define PxIN P0
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#define PxDIR P0DIR
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#define PxSEL P0SEL
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#define UxCSR U0CSR
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#define UxUCR U0UCR
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#define UxDBUF U0DBUF
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#define UxBAUD U0BAUD
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#define UxGCR U0GCR
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#define URXxIE URX0IE
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#define URXxIF URX0IF
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#define UTXxIE UTX0IE
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#define UTXxIF UTX0IF
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#else
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#define PxOUT P1
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#define PxIN P1
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#define PxDIR P1DIR
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#define PxSEL P1SEL
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#define UxCSR U1CSR
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#define UxUCR U1UCR
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#define UxDBUF U1DBUF
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#define UxBAUD U1BAUD
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#define UxGCR U1GCR
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#define URXxIE URX1IE
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#define URXxIF URX1IF
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#define UTXxIE UTX1IE
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#define UTXxIF UTX1IF
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#endif
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#if (HAL_UART_DMA == 1)
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#define HAL_UART_PERCFG_BIT 0x01 // USART0 on P0, Alt-1; so clear this bit.
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#define HAL_UART_Px_RX_TX 0x0C // Peripheral I/O Select for Rx/Tx.
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#define HAL_UART_Px_RTS 0x20 // Peripheral I/O Select for RTS.
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#define HAL_UART_Px_CTS 0x10 // Peripheral I/O Select for CTS.
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#else
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#define HAL_UART_PERCFG_BIT 0x02 // USART1 on P1, Alt-2; so set this bit.
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#define HAL_UART_Px_RTS 0x20 // Peripheral I/O Select for RTS.
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#define HAL_UART_Px_CTS 0x10 // Peripheral I/O Select for CTS.
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#define HAL_UART_Px_RX_TX 0xC0 // Peripheral I/O Select for Rx/Tx.
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#endif
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// The timeout tick is at 32-kHz, so multiply msecs by 33.
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#define HAL_UART_MSECS_TO_TICKS 33
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#if defined MT_TASK
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#define HAL_UART_DMA_TX_MAX MT_UART_DEFAULT_MAX_TX_BUFF
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#define HAL_UART_DMA_RX_MAX MT_UART_DEFAULT_MAX_RX_BUFF
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#define HAL_UART_DMA_HIGH MT_UART_DEFAULT_THRESHOLD
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#define HAL_UART_DMA_IDLE (MT_UART_DEFAULT_IDLE_TIMEOUT * HAL_UART_MSECS_TO_TICKS)
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#else
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#if !defined HAL_UART_DMA_RX_MAX
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#define HAL_UART_DMA_RX_MAX 256
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#endif
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#if !defined HAL_UART_DMA_TX_MAX
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#define HAL_UART_DMA_TX_MAX HAL_UART_DMA_RX_MAX
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#endif
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#if !defined HAL_UART_DMA_HIGH
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#define HAL_UART_DMA_HIGH (HAL_UART_DMA_RX_MAX / 2 - 16)
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#endif
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#if !defined HAL_UART_DMA_IDLE
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#define HAL_UART_DMA_IDLE (1 * HAL_UART_MSECS_TO_TICKS)
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#endif
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#endif
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#if !defined HAL_UART_DMA_FULL
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#define HAL_UART_DMA_FULL (HAL_UART_DMA_RX_MAX - 16)
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#endif
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#if defined HAL_BOARD_CC2430EB || defined HAL_BOARD_CC2430DB || defined HAL_BOARD_CC2430BB
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#define HAL_DMA_U0DBUF 0xDFC1
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#define HAL_DMA_U1DBUF 0xDFF9
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#else /* CC2530 */
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#define HAL_DMA_U0DBUF 0x70C1
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#define HAL_DMA_U1DBUF 0x70F9
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#endif
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#if (HAL_UART_DMA == 1)
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#define DMATRIG_RX HAL_DMA_TRIG_URX0
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#define DMATRIG_TX HAL_DMA_TRIG_UTX0
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#define DMA_UDBUF HAL_DMA_U0DBUF
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#define DMA_PAD U0BAUD
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#else
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#define DMATRIG_RX HAL_DMA_TRIG_URX1
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#define DMATRIG_TX HAL_DMA_TRIG_UTX1
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#define DMA_UDBUF HAL_DMA_U1DBUF
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#define DMA_PAD U1BAUD
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#endif
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/*********************************************************************
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* TYPEDEFS
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*/
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#if HAL_UART_DMA_RX_MAX <= 256
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typedef uint8 rxIdx_t;
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#else
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typedef uint16 rxIdx_t;
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#endif
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#if HAL_UART_DMA_TX_MAX <= 256
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typedef uint8 txIdx_t;
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#else
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typedef uint16 txIdx_t;
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#endif
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typedef struct
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{
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uint16 rxBuf[HAL_UART_DMA_RX_MAX];
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rxIdx_t rxHead;
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rxIdx_t rxTail;
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uint8 rxTick;
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uint8 rxShdw;
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uint8 txBuf[2][HAL_UART_DMA_TX_MAX];
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txIdx_t txIdx[2];
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volatile uint8 txSel;
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uint8 txMT;
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uint8 txTick; // 1-character time in 32kHz ticks according to baud rate,
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// to be used in calculating time lapse since DMA ISR
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// to allow delay margin before start firing DMA, so that
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// DMA does not overwrite UART DBUF of previous packet
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volatile uint8 txShdw; // Sleep Timer LSB shadow.
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volatile uint8 txShdwValid; // TX shadow value is valid
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uint8 txDMAPending; // UART TX DMA is pending
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halUARTCBack_t uartCB;
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} uartDMACfg_t;
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/*********************************************************************
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* GLOBAL VARIABLES
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*/
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/*********************************************************************
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* GLOBAL FUNCTIONS
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*/
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void HalUARTIsrDMA(void);
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/*********************************************************************
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* LOCAL VARIABLES
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*/
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static uartDMACfg_t dmaCfg;
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/*********************************************************************
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* LOCAL FUNCTIONS
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*/
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static rxIdx_t findTail(void);
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// Invoked by functions in hal_uart.c when this file is included.
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static void HalUARTInitDMA(void);
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static void HalUARTOpenDMA(halUARTCfg_t *config);
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static uint16 HalUARTReadDMA(uint8 *buf, uint16 len);
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static uint16 HalUARTWriteDMA(uint8 *buf, uint16 len);
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static void HalUARTPollDMA(void);
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static uint16 HalUARTRxAvailDMA(void);
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static void HalUARTSuspendDMA(void);
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static void HalUARTResumeDMA(void);
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/*****************************************************************************
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* @fn findTail
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*
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* @brief Find the rxBuf index where the DMA RX engine is working.
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*
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* @param None.
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*
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* @return Index of tail of rxBuf.
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*****************************************************************************/
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static rxIdx_t findTail(void)
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{
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rxIdx_t idx = dmaCfg.rxHead;
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do
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{
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if (!HAL_UART_DMA_NEW_RX_BYTE(idx))
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{
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break;
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}
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#if HAL_UART_DMA_RX_MAX == 256
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idx++;
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#else
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if (++idx >= HAL_UART_DMA_RX_MAX)
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{
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idx = 0;
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}
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#endif
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} while (idx != dmaCfg.rxHead);
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return idx;
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}
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/******************************************************************************
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* @fn HalUARTInitDMA
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*
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* @brief Initialize the UART
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*
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* @param none
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*
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* @return none
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*****************************************************************************/
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static void HalUARTInitDMA(void)
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{
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halDMADesc_t *ch;
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P2DIR &= ~P2DIR_PRIPO;
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P2DIR |= HAL_UART_PRIPO;
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#if (HAL_UART_DMA == 1)
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PERCFG &= ~HAL_UART_PERCFG_BIT; // Set UART0 I/O to Alt. 1 location on P0.
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#else
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PERCFG |= HAL_UART_PERCFG_BIT; // Set UART1 I/O to Alt. 2 location on P1.
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#endif
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PxSEL |= HAL_UART_Px_RX_TX; // Enable Tx and Rx on P1.
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ADCCFG &= ~HAL_UART_Px_RX_TX; // Make sure ADC doesnt use this.
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UxCSR = CSR_MODE; // Mode is UART Mode.
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UxUCR = UCR_FLUSH; // Flush it.
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// Setup Tx by DMA.
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ch = HAL_DMA_GET_DESC1234( HAL_DMA_CH_TX );
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// The start address of the destination.
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HAL_DMA_SET_DEST( ch, DMA_UDBUF );
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// Using the length field to determine how many bytes to transfer.
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HAL_DMA_SET_VLEN( ch, HAL_DMA_VLEN_USE_LEN );
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// One byte is transferred each time.
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HAL_DMA_SET_WORD_SIZE( ch, HAL_DMA_WORDSIZE_BYTE );
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// The bytes are transferred 1-by-1 on Tx Complete trigger.
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HAL_DMA_SET_TRIG_MODE( ch, HAL_DMA_TMODE_SINGLE );
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HAL_DMA_SET_TRIG_SRC( ch, DMATRIG_TX );
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// The source address is incremented by 1 byte after each transfer.
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HAL_DMA_SET_SRC_INC( ch, HAL_DMA_SRCINC_1 );
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// The destination address is constant - the Tx Data Buffer.
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HAL_DMA_SET_DST_INC( ch, HAL_DMA_DSTINC_0 );
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// The DMA Tx done is serviced by ISR in order to maintain full thruput.
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HAL_DMA_SET_IRQ( ch, HAL_DMA_IRQMASK_ENABLE );
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// Xfer all 8 bits of a byte xfer.
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HAL_DMA_SET_M8( ch, HAL_DMA_M8_USE_8_BITS );
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// DMA has highest priority for memory access.
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HAL_DMA_SET_PRIORITY( ch, HAL_DMA_PRI_HIGH );
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// Setup Rx by DMA.
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ch = HAL_DMA_GET_DESC1234( HAL_DMA_CH_RX );
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// The start address of the source.
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HAL_DMA_SET_SOURCE( ch, DMA_UDBUF );
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// Using the length field to determine how many bytes to transfer.
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HAL_DMA_SET_VLEN( ch, HAL_DMA_VLEN_USE_LEN );
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/* The trick is to cfg DMA to xfer 2 bytes for every 1 byte of Rx.
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* The byte after the Rx Data Buffer is the Baud Cfg Register,
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* which always has a known value. So init Rx buffer to inverse of that
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* known value. DMA word xfer will flip the bytes, so every valid Rx byte
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* in the Rx buffer will be preceded by a DMA_PAD char equal to the
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* Baud Cfg Register value.
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*/
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HAL_DMA_SET_WORD_SIZE( ch, HAL_DMA_WORDSIZE_WORD );
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// The bytes are transferred 1-by-1 on Rx Complete trigger.
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HAL_DMA_SET_TRIG_MODE( ch, HAL_DMA_TMODE_SINGLE_REPEATED );
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HAL_DMA_SET_TRIG_SRC( ch, DMATRIG_RX );
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// The source address is constant - the Rx Data Buffer.
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HAL_DMA_SET_SRC_INC( ch, HAL_DMA_SRCINC_0 );
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// The destination address is incremented by 1 word after each transfer.
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HAL_DMA_SET_DST_INC( ch, HAL_DMA_DSTINC_1 );
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HAL_DMA_SET_DEST( ch, dmaCfg.rxBuf );
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HAL_DMA_SET_LEN( ch, HAL_UART_DMA_RX_MAX );
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// The DMA is to be polled and shall not issue an IRQ upon completion.
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HAL_DMA_SET_IRQ( ch, HAL_DMA_IRQMASK_DISABLE );
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// Xfer all 8 bits of a byte xfer.
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HAL_DMA_SET_M8( ch, HAL_DMA_M8_USE_8_BITS );
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// DMA has highest priority for memory access.
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HAL_DMA_SET_PRIORITY( ch, HAL_DMA_PRI_HIGH );
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}
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/******************************************************************************
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* @fn HalUARTOpenDMA
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*
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* @brief Open a port according tp the configuration specified by parameter.
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*
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* @param config - contains configuration information
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*
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* @return none
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*****************************************************************************/
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static void HalUARTOpenDMA(halUARTCfg_t *config)
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{
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dmaCfg.uartCB = config->callBackFunc;
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// Only supporting subset of baudrate for code size - other is possible.
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HAL_UART_ASSERT((config->baudRate == HAL_UART_BR_9600) ||
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(config->baudRate == HAL_UART_BR_19200) ||
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(config->baudRate == HAL_UART_BR_38400) ||
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(config->baudRate == HAL_UART_BR_57600) ||
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(config->baudRate == HAL_UART_BR_115200));
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if (config->baudRate == HAL_UART_BR_57600 ||
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config->baudRate == HAL_UART_BR_115200)
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{
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UxBAUD = 216;
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}
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else
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{
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UxBAUD = 59;
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}
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switch (config->baudRate)
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{
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case HAL_UART_BR_9600:
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UxGCR = 8;
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dmaCfg.txTick = 35; // (32768Hz / (9600bps / 10 bits))
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// 10 bits include start and stop bits.
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break;
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case HAL_UART_BR_19200:
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UxGCR = 9;
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dmaCfg.txTick = 18;
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break;
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case HAL_UART_BR_38400:
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UxGCR = 10;
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dmaCfg.txTick = 9;
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break;
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|
case HAL_UART_BR_57600:
|
|
UxGCR = 10;
|
|
dmaCfg.txTick = 6;
|
|
break;
|
|
default:
|
|
// HAL_UART_BR_115200
|
|
UxGCR = 11;
|
|
dmaCfg.txTick = 3;
|
|
break;
|
|
}
|
|
|
|
// 8 bits/char; no parity; 1 stop bit; stop bit hi.
|
|
if (config->flowControl)
|
|
{
|
|
UxUCR = UCR_FLOW | UCR_STOP;
|
|
PxSEL |= HAL_UART_Px_CTS;
|
|
// DMA Rx is always on (self-resetting). So flow must be controlled by the S/W polling the Rx
|
|
// buffer level. Start by allowing flow.
|
|
PxOUT &= ~HAL_UART_Px_RTS;
|
|
PxDIR |= HAL_UART_Px_RTS;
|
|
}
|
|
else
|
|
{
|
|
UxUCR = UCR_STOP;
|
|
}
|
|
|
|
dmaCfg.rxBuf[0] = *(volatile uint8 *)DMA_UDBUF; // Clear the DMA Rx trigger.
|
|
HAL_DMA_CLEAR_IRQ(HAL_DMA_CH_RX);
|
|
HAL_DMA_ARM_CH(HAL_DMA_CH_RX);
|
|
osal_memset(dmaCfg.rxBuf, (DMA_PAD ^ 0xFF), HAL_UART_DMA_RX_MAX*2);
|
|
|
|
UxCSR |= CSR_RE;
|
|
|
|
// Initialize that TX DMA is not pending
|
|
dmaCfg.txDMAPending = FALSE;
|
|
dmaCfg.txShdwValid = FALSE;
|
|
}
|
|
|
|
/*****************************************************************************
|
|
* @fn HalUARTReadDMA
|
|
*
|
|
* @brief Read a buffer from the UART
|
|
*
|
|
* @param buf - valid data buffer at least 'len' bytes in size
|
|
* len - max length number of bytes to copy to 'buf'
|
|
*
|
|
* @return length of buffer that was read
|
|
*****************************************************************************/
|
|
static uint16 HalUARTReadDMA(uint8 *buf, uint16 len)
|
|
{
|
|
uint16 cnt;
|
|
|
|
for (cnt = 0; cnt < len; cnt++)
|
|
{
|
|
if (!HAL_UART_DMA_NEW_RX_BYTE(dmaCfg.rxHead))
|
|
{
|
|
break;
|
|
}
|
|
*buf++ = HAL_UART_DMA_GET_RX_BYTE(dmaCfg.rxHead);
|
|
HAL_UART_DMA_CLR_RX_BYTE(dmaCfg.rxHead);
|
|
#if HAL_UART_DMA_RX_MAX == 256
|
|
(dmaCfg.rxHead)++;
|
|
#else
|
|
if (++(dmaCfg.rxHead) >= HAL_UART_DMA_RX_MAX)
|
|
{
|
|
dmaCfg.rxHead = 0;
|
|
}
|
|
#endif
|
|
}
|
|
PxOUT &= ~HAL_UART_Px_RTS; // Re-enable the flow on any read.
|
|
|
|
return cnt;
|
|
}
|
|
|
|
/******************************************************************************
|
|
* @fn HalUARTWriteDMA
|
|
*
|
|
* @brief Write a buffer to the UART.
|
|
*
|
|
* @param buf - pointer to the buffer that will be written, not freed
|
|
* len - length of
|
|
*
|
|
* @return length of the buffer that was sent
|
|
*****************************************************************************/
|
|
static uint16 HalUARTWriteDMA(uint8 *buf, uint16 len)
|
|
{
|
|
uint16 cnt;
|
|
halIntState_t his;
|
|
uint8 txSel;
|
|
txIdx_t txIdx;
|
|
|
|
// Enforce all or none.
|
|
if ((len + dmaCfg.txIdx[dmaCfg.txSel]) > HAL_UART_DMA_TX_MAX)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
HAL_ENTER_CRITICAL_SECTION(his);
|
|
txSel = dmaCfg.txSel;
|
|
txIdx = dmaCfg.txIdx[txSel];
|
|
HAL_EXIT_CRITICAL_SECTION(his);
|
|
|
|
for (cnt = 0; cnt < len; cnt++)
|
|
{
|
|
dmaCfg.txBuf[txSel][txIdx++] = buf[cnt];
|
|
}
|
|
|
|
HAL_ENTER_CRITICAL_SECTION(his);
|
|
if (txSel != dmaCfg.txSel)
|
|
{
|
|
HAL_EXIT_CRITICAL_SECTION(his);
|
|
txSel = dmaCfg.txSel;
|
|
txIdx = dmaCfg.txIdx[txSel];
|
|
|
|
for (cnt = 0; cnt < len; cnt++)
|
|
{
|
|
dmaCfg.txBuf[txSel][txIdx++] = buf[cnt];
|
|
}
|
|
HAL_ENTER_CRITICAL_SECTION(his);
|
|
}
|
|
|
|
dmaCfg.txIdx[txSel] = txIdx;
|
|
|
|
if (dmaCfg.txIdx[(txSel ^ 1)] == 0)
|
|
{
|
|
// TX DMA is expected to be fired
|
|
dmaCfg.txDMAPending = TRUE;
|
|
}
|
|
HAL_EXIT_CRITICAL_SECTION(his);
|
|
return cnt;
|
|
}
|
|
|
|
/******************************************************************************
|
|
* @fn HalUARTPollDMA
|
|
*
|
|
* @brief Poll a USART module implemented by DMA.
|
|
*
|
|
* @param none
|
|
*
|
|
* @return none
|
|
*****************************************************************************/
|
|
static void HalUARTPollDMA(void)
|
|
{
|
|
uint16 cnt = 0;
|
|
uint8 evt = 0;
|
|
|
|
if (HAL_UART_DMA_NEW_RX_BYTE(dmaCfg.rxHead))
|
|
{
|
|
rxIdx_t tail = findTail();
|
|
|
|
// If the DMA has transferred in more Rx bytes, reset the Rx idle timer.
|
|
if (dmaCfg.rxTail != tail)
|
|
{
|
|
dmaCfg.rxTail = tail;
|
|
|
|
// Re-sync the shadow on any 1st byte(s) received.
|
|
if (dmaCfg.rxTick == 0)
|
|
{
|
|
dmaCfg.rxShdw = ST0;
|
|
}
|
|
dmaCfg.rxTick = HAL_UART_DMA_IDLE;
|
|
}
|
|
else if (dmaCfg.rxTick)
|
|
{
|
|
// Use the LSB of the sleep timer (ST0 must be read first anyway).
|
|
uint8 decr = ST0 - dmaCfg.rxShdw;
|
|
|
|
if (dmaCfg.rxTick > decr)
|
|
{
|
|
dmaCfg.rxTick -= decr;
|
|
dmaCfg.rxShdw = ST0;
|
|
}
|
|
else
|
|
{
|
|
dmaCfg.rxTick = 0;
|
|
}
|
|
}
|
|
cnt = HalUARTRxAvailDMA();
|
|
}
|
|
else
|
|
{
|
|
dmaCfg.rxTick = 0;
|
|
}
|
|
|
|
if (cnt >= HAL_UART_DMA_FULL)
|
|
{
|
|
evt = HAL_UART_RX_FULL;
|
|
}
|
|
else if (cnt >= HAL_UART_DMA_HIGH)
|
|
{
|
|
evt = HAL_UART_RX_ABOUT_FULL;
|
|
PxOUT |= HAL_UART_Px_RTS; // Disable Rx flow.
|
|
}
|
|
else if (cnt && !dmaCfg.rxTick)
|
|
{
|
|
evt = HAL_UART_RX_TIMEOUT;
|
|
}
|
|
|
|
if (dmaCfg.txMT)
|
|
{
|
|
dmaCfg.txMT = FALSE;
|
|
evt |= HAL_UART_TX_EMPTY;
|
|
}
|
|
|
|
if (dmaCfg.txShdwValid)
|
|
{
|
|
uint8 decr = ST0;
|
|
decr -= dmaCfg.txShdw;
|
|
if (decr > dmaCfg.txTick)
|
|
{
|
|
// No protection for txShdwValid is required
|
|
// because while the shadow was valid, DMA ISR cannot be triggered
|
|
// to cause concurrent access to this variable.
|
|
dmaCfg.txShdwValid = FALSE;
|
|
}
|
|
}
|
|
|
|
if (dmaCfg.txDMAPending && !dmaCfg.txShdwValid)
|
|
{
|
|
// UART TX DMA is expected to be fired and enough time has lapsed since last DMA ISR
|
|
// to know that DBUF can be overwritten
|
|
halDMADesc_t *ch = HAL_DMA_GET_DESC1234(HAL_DMA_CH_TX);
|
|
halIntState_t intState;
|
|
|
|
// Clear the DMA pending flag
|
|
dmaCfg.txDMAPending = FALSE;
|
|
|
|
HAL_DMA_SET_SOURCE(ch, dmaCfg.txBuf[dmaCfg.txSel]);
|
|
HAL_DMA_SET_LEN(ch, dmaCfg.txIdx[dmaCfg.txSel]);
|
|
dmaCfg.txSel ^= 1;
|
|
HAL_ENTER_CRITICAL_SECTION(intState);
|
|
HAL_DMA_ARM_CH(HAL_DMA_CH_TX);
|
|
do
|
|
{
|
|
asm("NOP");
|
|
} while (!HAL_DMA_CH_ARMED(HAL_DMA_CH_TX));
|
|
HAL_DMA_CLEAR_IRQ(HAL_DMA_CH_TX);
|
|
HAL_DMA_MAN_TRIGGER(HAL_DMA_CH_TX);
|
|
HAL_EXIT_CRITICAL_SECTION(intState);
|
|
}
|
|
else
|
|
{
|
|
halIntState_t his;
|
|
|
|
HAL_ENTER_CRITICAL_SECTION(his);
|
|
if ((dmaCfg.txIdx[dmaCfg.txSel] != 0) && !HAL_DMA_CH_ARMED(HAL_DMA_CH_TX)
|
|
&& !HAL_DMA_CHECK_IRQ(HAL_DMA_CH_TX))
|
|
{
|
|
HAL_EXIT_CRITICAL_SECTION(his);
|
|
HalUARTIsrDMA();
|
|
}
|
|
else
|
|
{
|
|
HAL_EXIT_CRITICAL_SECTION(his);
|
|
}
|
|
}
|
|
|
|
if (evt && (dmaCfg.uartCB != NULL))
|
|
{
|
|
dmaCfg.uartCB(HAL_UART_DMA-1, evt);
|
|
}
|
|
}
|
|
|
|
/**************************************************************************************************
|
|
* @fn HalUARTRxAvailDMA()
|
|
*
|
|
* @brief Calculate Rx Buffer length - the number of bytes in the buffer.
|
|
*
|
|
* @param none
|
|
*
|
|
* @return length of current Rx Buffer
|
|
**************************************************************************************************/
|
|
static uint16 HalUARTRxAvailDMA(void)
|
|
{
|
|
uint16 cnt = 0;
|
|
|
|
if (HAL_UART_DMA_NEW_RX_BYTE(dmaCfg.rxHead))
|
|
{
|
|
uint16 idx;
|
|
|
|
for (idx = 0; idx < HAL_UART_DMA_RX_MAX; idx++)
|
|
{
|
|
if (HAL_UART_DMA_NEW_RX_BYTE(idx))
|
|
{
|
|
cnt++;
|
|
}
|
|
}
|
|
}
|
|
|
|
return cnt;
|
|
}
|
|
|
|
/******************************************************************************
|
|
* @fn HalUARTSuspendDMA
|
|
*
|
|
* @brief Suspend UART hardware before entering PM mode 1, 2 or 3.
|
|
*
|
|
* @param None
|
|
*
|
|
* @return None
|
|
*****************************************************************************/
|
|
static void HalUARTSuspendDMA( void )
|
|
{
|
|
PxOUT |= HAL_UART_Px_RTS; // Disable Rx flow.
|
|
UxCSR &= ~CSR_RE;
|
|
P0IEN |= HAL_UART_Px_CTS; // Enable the CTS ISR.
|
|
}
|
|
|
|
/******************************************************************************
|
|
* @fn HalUARTResumeDMA
|
|
*
|
|
* @brief Resume UART hardware after exiting PM mode 1, 2 or 3.
|
|
*
|
|
* @param None
|
|
*
|
|
* @return None
|
|
*****************************************************************************/
|
|
static void HalUARTResumeDMA( void )
|
|
{
|
|
P0IEN &= ~HAL_UART_Px_CTS; // Disable the CTS ISR.
|
|
UxUCR |= UCR_FLUSH;
|
|
UxCSR |= CSR_RE;
|
|
PxOUT &= ~HAL_UART_Px_RTS; // Re-enable Rx flow.
|
|
}
|
|
|
|
/******************************************************************************
|
|
* @fn HalUARTIsrDMA
|
|
*
|
|
* @brief Handle the Tx done DMA ISR.
|
|
*
|
|
* @param none
|
|
*
|
|
* @return none
|
|
*****************************************************************************/
|
|
void HalUARTIsrDMA(void);
|
|
void HalUARTIsrDMA(void)
|
|
{
|
|
HAL_DMA_CLEAR_IRQ(HAL_DMA_CH_TX);
|
|
|
|
// Indicate that the other buffer is free now.
|
|
dmaCfg.txIdx[(dmaCfg.txSel ^ 1)] = 0;
|
|
dmaCfg.txMT = TRUE;
|
|
|
|
// Set TX shadow
|
|
dmaCfg.txShdw = ST0;
|
|
dmaCfg.txShdwValid = TRUE;
|
|
|
|
// If there is more Tx data ready to go, re-start the DMA immediately on it.
|
|
if (dmaCfg.txIdx[dmaCfg.txSel])
|
|
{
|
|
// UART TX DMA is expected to be fired
|
|
dmaCfg.txDMAPending = TRUE;
|
|
}
|
|
}
|
|
|
|
/******************************************************************************
|
|
******************************************************************************/
|